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UP9303 1 UP9303-ds-f0101, aug. 2017 www.upi-semi.com 5v/12v synchronous-rectified buck controller the UP9303 is a compact synchronous-rectified buck controller specifically designed to operate with single 12v supply voltage and to deliver high quality output voltage. it adopts external compensated, voltage mode control to tightly regulate the feedback votlage to internal 0.6v reference voltage. the switching frequency is programmable from 50khz to 500khz, providing an optimal level of integration to reduce size and cost of the power supply. the UP9303 integrates mosfet drivers that support 12v+12v bootstrapped voltage for high efficiency power conversion. the UP9303b features clock output that enables synchronized operation of two buck converters, reducing stress at input capacitors and emi interference between converters. other features include under voltage lockout (uvlo), under- voltage protection, over-voltage protection and user programmable over-current protection. with aforementioned functions, this part provides customers a compact, high efficiency, well-protected and cost-effective solutions. this part is available in sop-14l package. operate with single 12v supply voltage 0.6v v ref with 1.0% accuracy up to 30a high output current lossless, programmable overcurrent protection uses upper mosfet r ds(on) adjustable soft start support synchronized operation clock output (UP9303b) simple voltage-mode pwm control design adjustable switching frequency external compensation fast transient response minimum off time 300ns adaptive shoot-through protection over/under voltage protection rohs compliant and halogen free rebmunredr oe pytegakca pg nikram pot casa3039p ul 41-po sa 3039pu casb3039p ul 41-po sb 3039pu general description ordering information features cable modems, set top boxes, and xdsl modems atx power supplies power supplies for microprocessors or subsystem power supplies industrial power supplies; general purpose supplies 5v or 12v input dc-dc regulators low voltage distributed power supplies applications pin configuration note: upi products are compatible with the current ipc/ jedec j-std-020 requirement. they are halogen-free, rohs compliant and 100% matte tin (sn) plating that are suitable for use in snpb or pb-free soldering processes. vcc fset/syn pvcc lgate pgnd ocset ss comp 12 3 41 1 12 13 14 UP9303a boot ugate phase fb en gnd 56 78 9 10 vcc fset/syn pvcc lgate pgnd ocset ss comp UP9303b boot ugate phase fb clk gnd 12 3 41 1 12 13 14 56 78 9 10
UP9303 2 UP9303-ds-f0101, aug. 2017 www.upi-semi.com typical application circuit 12v vcc fset/syn pvcc lgate pgnd ss comp boot ugate phase fb clk gnd v out1 12v vcc fset/syn pvcc lgate pgnd ocset ss comp boot ugate phase fb en/(clk) gnd v in v out2 UP9303b UP9303a/b r1 r2 master slave ocset v in
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UP9303 4 UP9303-ds-f0101, aug. 2017 www.upi-semi.com functional block diagram power on reset soft start oscillator pwm pvcc pvcc pgnd lgate boot gate control logic phase ugate ocset vcc en (UP9303a) fb gnd ss comp fset/syn 0.6v 0.3v ocp comparator uvp comparator 200ua 30ua -1.8v x1/2 5vdd 0.78v ovp comparator error amp. sse UP9303a power on reset soft start oscillator pwm pvcc pvcc pgnd lgate boot gate control logic phase ugate ocset vcc fb gnd ss comp clk (UP9303b) fset/syn 0.6v 0.3v ocp comparator uvp comparator 200ua 30ua -1.8v x1/2 5vdd 0.78v ovp comparator error amp. sse UP9303b
UP9303 5 UP9303-ds-f0101, aug. 2017 www.upi-semi.com the UP9303 is a compact synchronous-rectified buck controller specifically designed to operate with single 12v supply voltage and to deliver high quality output voltage. it adopts external compensated, voltage mode control to tightly regulate the feedback votlage to internal 0.6v reference voltage. the switching frequency is programmable from 50khz to 500khz, providing an optimal level of integration to reduce size and cost of the power supply. the UP9303 integrates mosfet drivers that support 12v+12v bootstrapped voltage for high efficiency power conversion. the UP9303b features clock output that enables synchronized operation of two buck converters, reducing stress at input capacitors and emi interference between converters. other features include under voltage lockout (uvlo), under- voltage protection, over-voltage protection and user programmable over-current protection. with aforementioned functions, this part provides customers a compact, high efficiency, well-protected and cost-effective solutions. this part is available in sop-14 package. supply voltage the UP9303 features two supply input pins: vcc and pvcc for control circuit and gate drivers respectively. in real application, connect vcc and pvcc to a well-decoupled 10.8v to 13.2v supply voltage as shown in the typical application circuit . a minimum 1uf ceramic capacitor physically near the supply input pins are required for locally bypassing the supply voltages. an internal linear regulator regulates vcc supply voltage into a 5.0v voltage 5vdd for internal control logic circuit. no external bypass capacitor is required for filtering the 5vdd voltage. the UP9303 integrates mosfet gate drives that are powered from the pvcc pin and support 12v+12v driving capability. converters that consist of UP9303 feature high efficiency without special consideration on the selection of mosfets. power on reset and chip enable the UP9303 continuously monitors 1.) vcc pin voltage, 2.) en pin voltage, 3.) ocset pin voltage and 4.) fset/ syn pin voltage for power on reset. the UP9303 is enabled only when all the por is released. the por threshold voltage are 9.5v, 1.3v, 1.3v and 0.4v at vcc, en, ocset, and fset/syn rising respectively. before por is released, the UP9303 is disabled, ss pin is pulled low to ground and both gate drivers are turned off. because the pvcc voltage is not monitored by por circuitry, it must be connected to vcc pin externally to ensure pvcc is ready when por is released. soft start a capacitor c ss connected to ss pin controls the soft start behavior of output voltage as shown in figure 1. before por is released, the ss pin is internally pulled low to ground. when por is released, an internal 30ua current source starts to charge c ss , resulting in a linearly ramping-up voltage v ss : t c ua 30 v ss ss = v fb v ss v out tim e voltage 4.2v 1.8v 0.6v t0 t1 t2 figure 1. softstart behavior. the error amplifier is a three-input device (referring to the functional block diagram). reference voltage v ref or the soft start voltage v sse whichever is smaller dominates the behavior of the non-inverting input of the error amplifier. the sse voltage is clamped as: 4 v8.1 c/t ua 30 4 v8.1 v v ss ss sse = = consequently, when v ss is lower than 1.8v, the feedback voltage v fb is kept at zero. when v ss is between 1.8v and 4.2v, the feedback voltage v fb ramps up linearly from 0v to 0.6v. when v ss is higher than 4.2v, the internal 0.6v reference takes over the control of error amplifier and the feedback voltage is regulated to v ref . at the same time, the UP9303 asserts soft start end and enables the under voltage protection. the output voltage ramp-up time can be calculated as: ua 30 c v4.2 i c )v8.1 v2.4( 1t 2t t ss ss ss ss = = = switching frequency settingthe UP9303 features adjustable switching frequency by a resistor connected to the fset/syn pin. when the fset/ syn pin is floating, the UP9303 operates at a free-running functional description
UP9303 6 UP9303-ds-f0101, aug. 2017 www.upi-semi.com 200khz switching frequency. when a resistor is connected from fset/syn to ground, the UP9303 operates at a frequency higher than 200khz. when a resistor is connected from fset/syn to vcc, the UP9303 operates at a frequency lower than 200khz. the figure 2 shows the relationship between switching frequency and the external resistance. r fset to gnd : ) k( ) 200 f( 9600 r sw fset ? = r fset to vcc : ) ( ) 200 ( 48000 ? = k f r sw fset 10 100 1000 10 100 1000 r fset to gnd r fset to vcc r fset (kohm) switching frequency(khz) figure 2. switching frequency vs. fset/syn resistance the switching frequency can also be synchronized to external clock from 50khz to 500mhz applied to fset/ syn pin. figure 4 depicts the clock logic of UP9303. when a resistor r fset is connected from fset/syn to gnd, its voltage v fset/syn is clamped to 2.4v. if the v fset/stn stays between 2.0v and 3.0v for 30us, the internal clock is selected for operation (local clock mode, lcm). a schmitt trigger circuit receives the v fset/syn and generates a inverse squarewave that is synchronized to the v fset/syn when a external clock or internal clock is applied. the UP9303 works with synchronization mode if the squarewave frequency is higher than 50khz (remote clock mode rcm). the v ih and v il of the schmitt trigger circuit are 2/3 and 1/3 of v cc respectively. if the v fset stays below 1/3 of 5vdd or above 2/3 of 5vdd for 30us, the UP9303 asserts clock off and turns off the converter (clock off mode com). the transitions from lcm to com, com to rcm or lcm to rcm are allowable. however, the transitions from com to lcm, rcm to com or rcm to lcm are regarded as fatal faults and not allowed. the UP9303 shuts down and latches off when forbidden mode transitions occur and can only be rest by por of v cc . the UP9303b outputs a clock signal at clk pin that is180 o out of phase with the operation clock. this clock can be used as synchronization for other upi controller that features fset/syn pin. output voltage setting the output voltage can be programmed by a resistive divider connected to the fb pin as shown in the typical application circuit: 1 r 2 r 1r v6.0 v out + = overcurrent protection (ocp) the UP9303 monitors the voltage drop across the upper mosfet for over current protection (ocp). a resistor connected between ocset pin and the drain of the upper mosfet programs the ocp threshold level as shown in the figrue 3. an internal 200ua current source flows through the r ocset , creating a voltage v ocset at ocset as: ocse t in ocset r ua 200 v v = phase ocset ocp comparator 200ua r ocset v in v out c ocset figure 3. ocp level programming. the ocp comparator compares the v ocset and v phase for over current protection when the upper mosfet turns on. if v phase is lower than v ocset , an ocp is triggered. the ocp threshold level is given by: ) on ( ds ocset ) on ( ds ocset ocset ocp r r ua 200 r r i i = = functional description
UP9303 7 UP9303-ds-f0101, aug. 2017 www.upi-semi.com an ocp will shut down the device and discharge the c ss with a 30ua sinking current source. when the c ss is discharged completely, another soft start cycle is initiated. if the over current condition is not removed during the soft start cycle, the UP9303 will shut down immediately when another ocp is triggered. however, the v ss keeps rising to 4v to complete the soft start cycle before theinternal 30ua current source discharges the c ss . if the over current conditon is not removed, the re-soft-start cycle will repeat 3 times and then latch off UP9303. to avoid false trigger of ocp, variations of all parameters in above equation should be well considered, including: 1.) the r ds(on) of mosfet varies with temperature and the gate to source voltage. consider the highest operation temperature and lowest gate to source voltage. 2.) consider the minimum i ocset (~180ua) and minimum r ocset . 3.) consider the inductor ripple current. functional description 2.4v current limited local clock generator clock logic clock logic remote clock (rc): rc frequency > 50khz local clock (lc): 2v < v fset < 3v for 30us clock off: otherwise ramp generator sampled and held current ramp fset/syn clk to turn off the current source when rc = 1 for local clock for remote clock under voltage protection (uvp) the fb voltage is monitored for undervoltage protection after soft start end is asserted. if the fb voltage is lower than 0.3v (50% of 0.6v reference voltage), the uvp is triggered and shuts down the UP9303 with about 10us time delay. the UP9303 turns off both upper and lower mosfets when uvp is triggered. the uvp is a latch-off type protection and can only be reset by por of the device. over voltage protection (ovp) the fb voltage is monitored for overvoltage protection. if the fb voltage is higher than 0.78v (130% of 0.6v reference voltage), the ovp is triggered and shuts down the UP9303 with about 10us time delay. the UP9303 turns off the upper and lower mosfet when ovp is triggered. the ovp is a latch-off type protection and can only be reset by por of the device. figure 4. clock logic of UP9303
UP9303 8 UP9303-ds-f0101, aug. 2017 www.upi-semi.com package thermal resistance (note 3) sop-14l ja ---------------------------------------------------------------------------------------------------------------- 120 o c/w sop-14l jc ------------------------------------------------------------------------------------------------------------------ 32 c/w power dissipation, p d @ t a = 25 c sop-14l ----------------------------------------------------------------------------------------------------------------------------- 0.83w (note 4) operating junction temperature ra nge --------------------------------------------------------------------- -40 c to +125 c operating ambient temperature ra nge ---------------------------------------------------------------------------------- -40 c to +85 c supply input voltage, v cc -------------------------------------------------------------------------------------------------- +10.8v to 13.2v absolute maximum rating thermal information recommended operation conditions (note 1) supply input voltage, v cc ---------------------------------------------------------------------------------------- -0.3v to +16v boot to phase dc ------------------------------------------------------------------------------------------------------------------------ -0.3v to +16v phase to gnd dc ------------------------------------------------------------------------------------------------------------------------ -0.7v to +16v <200ns --------------------------------------------------------------------------------------------------------------------- - 8v to +30v boot to gnd dc ----------------------------------------------------------------------------------------------------------------- -0.3v to (v cc +16v) <200ns ------------------------------------------------------------------------------------------------------------------- -0. 3v to 42v ugate to phase dc --------------------------------------------------------------------------------------------- -0.3v to (boot - phase + 0.3v ) <200ns ----------------------------------------------------------------------------------------- -5v to (boot - phase + 0.3v) lgate to gnd dc -------------------------------------------------------------------------------------------------------------- -0.3v to (v cc + 0.3v) <200ns ---------------------------------------------------------------------------------------------------------- -5v to (v cc + 0.3v) fb to gnd dc ---------------------------------------------------------------------------------------------------------------------- -0.3v to +7v <2ms ------------------------------------------------------------------------------------------------------------------ -0.7v fset/syn,ocset to gnd ---------------------------------------------------------------------------------- -0.3v to (v cc + 0.3v) comp to gnd ----------------------------------------------------------------------------------------------------------- -0.3v t o +7v en to gnd ------------------------------------------------------------------------------------------------------------------- - 0.3v to +16v clk,ss to gnd ----------------------------------------------------------------------------------------------------------------- - -0.3v to +6v pgnd to gnd --------------------------------------------------------------------------------------------------------------- -0. 3v to +0.3v storage temperature range ---------------------------------------------------------------------------------------------- -65 o c to +150 o c junction temperature -------------------------------------------------------------------------------------------------------------------- 150 o c lead temperature (soldering, 10 sec) ------------------------------------------------------------------------------------------------ 260 o c esd rating (note 2) hbm (human body mode) -------------------------------------------------------------------------------------------------------- 2kv mm (machine mode) ---------------------------------------------------------------------------------------------------------------- 200v
UP9303 9 UP9303-ds-f0101, aug. 2017 www.upi-semi.com retemara pl obmy ss noitidnoctse tn i mp y tx am s tinu tupniylppus egnaregatlovylppu sv cc 8.0 1- -2 .3 1v tnerructupniylppu si q_cc gnihctiws;nepo gl,g u- -50 1a m teser norewop dlohserhtgnisir rop cc vv htrcc v cc gnisi r0 . 95 . 90 .0 1v dlohserhtgnillafrop cc vv htfcc v cc )retsam(gnilla f5 . 675 . 7v v cc )evals(gnilla f5 . 70 . 85 . 8v dlohserhtroptesc ov tesco gnisi r- -3 . 1- -v siseretsyh roptesc ov tesco gnilla f- -1 . 0- -v dlohserhtrop n ev ne gnisi r- -3 . 1- -v siseretsyh rop n ev ne gnilla f- -1 . 0- -v rotallicso ycneuqerfgninnureer ff cso .nepo=tes f- -0 0 2- -z hk egatlovnip nys/tes fv nys/tesf .nepo=tes f- -4 . 2- -v ycaruccaycneuqerf 51 -- -5 1 +% egnartnemtsujdaycneuqerf 0 5- -0 0 5z hk egnarnoitazinorhcnysycnenqerf 0 5- -0 0 5z hk egnaroitarytudkcolclanretxe 0 1- -0 9% egatlov wolkcolclanretxe - -- -8 . 0v egatlovhgihkcolclanretxe 2. 4- -- -v edutilpmapmar ? v cso - -6 . 1- -v p-p emitffo mumimim - -0 0 3- -s n egatlovecnerefer ycaruccaegatlovecnerefe rv fer 495. 00 06. 06 06. 0v reifilpmarorre niag cdpoolnep oo an gisedybdeetnarau g0 70 8- -b d tcudorphtdiwdnab-nia gw b gn gisedybdeetnarau g- -0 1- -z hm etar wel sr sn gisedybdeetnarau g3 6 - -s u/v tnerructupnib fv bf v6.0 =- -1 0. 01a u egatlovhgih pmo cv h_pmoc - -5 . 5- -v egatlov wolpmo cv l_pmoc - -0- -v tnerrucecruos pmo cv pmoc v= h_pmoc v6.1 -- -2- -a m tnerrucknis pmo cv pmoc v6.1 =- -2- -a m (v cc = 12v, t a = 25 o c, unless otherwise specified) electrical characteristics
UP9303 10 UP9303-ds-f0101, aug. 2017 www.upi-semi.com retemara pl obmy ss noitidnoctse tn i mp y tx am s tinu tuptuo kcolc egatlovlevelhgihtuptu oi klc gnicruosam1 =5 . 4- -- -v egatlovlevelhgihtuptu oi klc gniknisam1 =- -- -4 . 0v oitarytudkcol cn epo=nys/tes f- -0 5- -% srevirdetagrellortnoc m w p tnerrucgnicruosetagrepp ui crs_gu v toob v,v21= etagu v- esahp v2 =- -5 . 2- - ecnatsiser gnicruosetagrepp ur crs_gu i gu gnicruosam001 =- -45 ? ecnatsisergniknisetagrepp ur kns_gu i gu gniknisam001 =- -23 ? tnerrucgnicruosetagrewo li crs_gl v ccvp v,v21= etagl v2 =- -5 . 6- -a ecnatsiser gnicruosetagrewo lr crs_gl i gl gnicruosam001 =- -5 . 15 .2 ? ecnatsisergniknisetagrewo lr kns_gl i gl gniknisam001 =- -12 ? yaledgnisir glotgnillafh pv hp votv2.1< gl v2.1 >- -5 2- -s n yaledgnisir guotgnillaf g lv gl v(otv2.1< gu v- hp v2.1> )- -5 2- -s n noitcetorp tnerrucegrahctrats-tfo si ss v ss v0 =4 20 36 3a u leveldlohserhtpv ov pvo v bf .gnisi r- -8 7. 0- -v emityaled pvo - -5 2- -s u leveldlohserhtpv uv pvu v bf gnilla f- -3 . 0- -v emityaled pvu - -2- -s u ecruostnerrucknistesc oi tesco v tesco v= cc .v3.0 -0 8 10 0 20 2 2a u emityaled pco - -5- -s u electrical characteristics note 1. stresses listed as the above absolute maximum ratings may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. devices are esd sensitive. handling precaution recommended. note 3. ja is measured in the natural convection at t a = 25 c on a low effective thermal conductivity test board of jedec 51-3 thermal measurement standard. note 4. the device is not guaranteed to function outside its operating conditions.
UP9303 11 UP9303-ds-f0101, aug. 2017 www.upi-semi.com typical operation characteristics ugate (20v/div) v out (5v/div) v ss (5v/div) vcc (5v/div) ugate (20v/div) v out (5v/div) v ss (5v/div) vcc (5v/div) output voltage vs. temperature temperature ( o c) output voltage variation (%) -1.8 -1.5 -1.2 -0.9 -0.6 -0.3 0.0 0.3 0.6 -40-20 0 20406080100120 frequency vs. temperature temperature ( o c) frequency (khz) 150 160 170 180 190 200 210 220 230 240 -40 -20 0 20 40 60 80 100 120 140 power off waveforms for UP9303a 40ms/div v in = v cc = 12v, no load power on waveforms for UP9303a 4ms/div v in = v cc = 12v, no load 25 26 27 28 29 30 31 -40 0 40 80 120 160 180 185 190 195 200 205 210 -40 0 40 80 120 160 i ocp vs. temperature temperature ( o c) i ocp (ua) i ss vs. temperature temperature ( o c) i ss (ua)
UP9303 12 UP9303-ds-f0101, aug. 2017 www.upi-semi.com ugate (20v/div) v out (2v/div) v ss (5v/div) vcc (10v/div) ugate (20v/div) v out (2v/div) v ss (5v/div) vcc (10v/div) ugatea (20v/div) ugateb (20v/div) v outa (2v/div) v outb (2v/div) ugatea (20v/div) ugateb (20v/div) v outa (2v/div) v outb (2v/div) typical operation characteristics power on waveforms for UP9303a/b 4ms/div v in = v cc = 12v, i load = 2a power off waveforms for UP9303a/b 4ms/div v in = v cc = 12v, i load = 2a en off waveforms for UP9303b 4ms/div v in = v cc = 12v, i load = 2a en on waveforms for UP9303b 4ms/div v in = v cc = 12v, i load = 2a ugate (20v/div) v out (5v/div) v ss (5v/div) clk (5v/div) ugate (20v/div) v out (5v/div) v ss (5v/div) clk (5v/div) power on waveforms for UP9303b 4ms/div v in = v cc = 12v, i load = 2a power off waveforms for UP9303b 40ms/div v in = v cc = 12v, i load = 2a
UP9303 13 UP9303-ds-f0101, aug. 2017 www.upi-semi.com ugatea (20v/div) ugateb (20v/div) clk (5v/div) v outb (2v/div) ugate (20v/div) lgate (20v/div) v out (2v/div) i out (10a/div) ugate (20v/div) lgate (20v/div) v out (2v/div) i out (10a/div) scp 20ms/div ocp 40ms/div typical operation characteristics operation mode for UP9303a/b 1us/div ugate (10v/div) phase (5v/div) lgate (5v/div) ugate-phase (10v/div) ugate (10v/div) phase (5v/div) lgate (5v/div) ugate-phase (10v/div) gate waveforms 40ns/div v in = v cc = 12v, i load = 10a gate waveforms 40ns/div v in = v cc = 12v, i load = 10a
UP9303 14 UP9303-ds-f0101, aug. 2017 www.upi-semi.com power mosfet selection external component selection is primarily determined by the maximum load current and begins with the selection of power mosfet switches. the UP9303 requires two external n-channel power mosfets for upper (controlled) and lower (synchronous) switches. important parameters for the power mosfets are the breakdown voltage v (br)dss , on-resistance r ds(on) , reverse transfer capacitance c rss , maximum current i ds(max) , gate supply requirements, and thermal management requirements. the gate drive voltage is powered by vcc pin that receives 10.8v~13.2v supply voltage. when operating with a 12v power supply for vcc (or down to a minimum supply voltage of 8v), a wide variety of nmosfets can be used. logic-level threshold mosfet should be used if the input voltage is expected to drop below 8v. since the lower mosfet is used as the current sensing element, particular attention must be paid to its on-resistance. look for r ds(on) ratings at lowest gate driving voltage. special cautions should be exercised on the lower switch exhibiting very low threshold voltage v gs(th) . the shoot- through protection present aboard the UP9303 may be circumvented by these mosfets if they have large parasitic impedances and/or capacitances that would inhibit the gate of the mosfet from being discharged below its threshold level before the complementary mosfet is turned on. also avoid mosfets with excessive switching times; the circuitry is expecting transitions to occur in under 50 nsec or so. in high-current applications, the mosfet power dissipation, package selection and heatsink are the dominant design factors. the power dissipation includes two loss components; conduction loss and switching loss. the conduction losses are the largest component of power dissipation for both the upper and the lower mosfets. these losses are distributed between the two mosfets according to duty cycle. since the UP9303 is operating in continuous conduction mode, the duty cycles for the mosfets are: in out up v v d = ; in out in lo v v v d = the resulting power dissipation in the mosfets at maximum output current are: os c sw in out up ) on ( ds 2 out up f t v i5.0 d r i p + = l o ) on ( ds 2 out lo d r i p = where t sw is the combined switch on and off time. application information both mosfets have i 2 r losses and the top mosfet includes an additional term for switching losses, which are largest at high input voltages. the bottom mosfet losses are greatest when the bottom duty cycle is near 88%, during a short-circuit or at high input voltage. these equations assume linear voltage current transitions and do not adequately model power loss due the reverse- recovery of the lower mosfets body diode. ensure that both mosfets are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal- resistance specifications. a separate heatsink may be necessary depending upon mosfet power, package type, ambient temperature and air flow. the gate-charge losses are dissipated by the UP9303 and dont heat the mosfets. however, large gate charge increases the switching interval, t sw that increases the mosfet switching losses. the gate-charge losses are calculated as: os c rss in lo _ iss up _ iss cc cc g f) c v ) c c( v( v p + + = where c iss_up is the input capacitance of the upper mosfet, c iss_lo is the input capacitance of the lower mosfet, and c rss_up is the reverse transfer capacitance of the upper mosfet. make sure that the gate-charge loss will not cause over temperature at UP9303, especially with large gate capacitance and high supply voltage. output inductor selection output inductor selection usually is based the considerations of inductance, rated current, size requirement, and dc resistance (dc) given the desired input and output voltages, the inductor value and operating frequency determine the ripple current: ) v v 1( v l f 1 i in out out out osc l = ? lower ripple current reduces core losses in the inductor, esr losses in the output capacitors and output voltage ripple. highest efficiency operation is obtained at low frequency with small ripple current. however, achieving this requires a large inductor. there is a tradeoff between component size, efficiency and operating frequency. a reasonable starting point is to choose a ripple current that is about 40% of i out(max) . there is another tradeoff between output ripple current/ voltage and response time to a transient load. increasing the value of inductance reduces the output ripple current and voltage. however, the large inductance values reduce the converters response time to a load transient. maximum current ratings of the inductor are generally
UP9303 15 UP9303-ds-f0101, aug. 2017 www.upi-semi.com specified in two methods: permissible dc current and saturation current. permissible dc current is the allowable dc current that causes 40 o c temperature raise. the saturation current is the allowable current that causes 10% inductance loss. make sure that the inductor will not saturate over the operation conditions including temperature range, input voltage range, and maximum output current. the size requirements refer to the area and height requirement for a particular design. for better efficiency, choose a low dc resistance inductor. dcr is usually inversely proportional to size. different core materials and shapes will change the size/ current and price/current relationship of an inductor. toroid or shielded pot cores in ferrite or permalloy materials are small and dont radi ate much energy, but generally cost more than powdered iron core inductors with similar electrical characteristics. the choice of which style inductor to use often depends more on the price vs. size requirements and any radiated field/emi requirements. input capacitor selection the synchronous-rectified buck converter draws pulsed current with sharp edges from the input capacitor resulting in ripples and spikes at the input supply voltage. use a mix of input bypass capacitors to control the voltage overshoot across the mosfets. use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time upper mosfet turns on. place the small ceramic capacitors physically close to the mosfets and between the drain of upper moset and the source of lower mosfet to avoid the stray inductance along the connection trace. the important parameters for the bulk input capacitor are the voltage rating and the rms current rating. for reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest rms current required by the circuit. the capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. the rms current rating requirement for the input capacitor of a buck converter is calculated as: in out in out ) max ( out ) rms ( in v ) v v( v i i = this formula has a maximum at v in = 2v out , where i in(rms) = i out(rms) /2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. note that the capacitor manufa cturers ri pple current ratings are often based on 2000 hours of life. this makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. always consult the manufacturer if there is any question. for a through-hole design, several electrolytic capacitors may be needed. for surface mount designs, solid tantalum capacitors can also be used, but caution must be exercised with regard to the capacitor surge current rating. these capacitors must be capable of handling the surge-current at power-up. some capacitor series available from reputable manufacturers are surge current tested. output capacitor selection an output capacitor is required to filter the output and supply the load transient current. the selection of c out is primarily determined by the esr required to minimize voltage ripple and load step transients. the output ripple ? v out is approximately bounded by: ) c f8 1 esr (i v out osc l out + ? ? since ? il increases with input voltage, the output ripple is highest at maximum input voltage. typically, once the esr requirement is satisfied, the capacitance is adequate for filtering and has the necessary rms current rating. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. special polymer capacitors offer very low esr but have lower capacitance density than other types. the load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. these requirements are generally met with a mix of capacitors and careful layout. modern components and loads are capable of producing transient load rates above 1a/ns. high frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. the bulk filter capacitor values are generally determined by the esr (effective series resistance) and voltage rating requirements rather than actual capacitance requirements. high frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. consult with the manufacturer of the load on specific decoupling requirements. use only specialized low-esr capacitors intended for application information
UP9303 16 UP9303-ds-f0101, aug. 2017 www.upi-semi.com switching-regulator applications for the bulk capacitors. the bulk capacitors esr will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. an aluminum electrolytic capa citors esr value is related to the case size with lower esr available in larger case sizes. however, the equivalent series inductance (esl) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. unfortunately, esl is not a specified parameter. work with your capacitor supplier and measure the capacitors impedance with frequency to select a suitable component. in most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor. bootstrap capacitor selection an external bootstrap capacitor c boot connected to the boot pin supplies the gate drive voltage for the upper mosfet. this capacitor is charged through the internal diode when the phase node is low. when the upper mosfet turns on, the phase node rises to v in and the boot pin rises to approximately v in + v cc . the boot capacitor needs to store about 100 times the gate charge required by the upper mosfet. in most applications 0.1uf to 0.47uf, x5r or x7r dielectric capacitor is adequate. pcb layout considerations high speed switching and relatively large peak currents in a synchronous-rectified buck converter make the pcb layout a very important part of design. fast current switching from one device to another in a synchronous- rectified buck converter causes voltage spikes across the interconnecting impedances and parasitic circuit elements. the voltage spikes can degrade efficiency and radiate noise that result in overvoltage stress on devices. careful component placement layout and printed circuit design minimizes the voltage spikes induced in the converter. follow the layout guidelines for optimal performance of UP9303 1 the upper and lower mosfets turn on/off and conduct pulsed current alternatively with high slew rate transition. any inductance in the switched current path generates a large voltage spike during the switching. the interconnecting wires indicated by red heavy lines conduct pulsed current with sharp transient and should be part of a ground or power plane in a printed circuit board to minimize the voltage spike. make all the connection the top layer with wide, copper filled areas. 2 place the power components as physically close as possible. 2.1 place the input capacitors, especially the high- frequency ceramic decoupling capacitors, directly to the drain of upper mosfet ad the source of the lower mosfet. to reduce the esr replace the single input capacitor with two parallel units 2.2 place the output capacitor between the converter and load. 3 place the UP9303 near the upper and lower mosfets with pins 1 to 4 facing the power components. keep the components connected to pins 4 to 8 close to the UP9303 and away from the inductor and other noise sources (noise sensitive components). 4 use a dedicated grounding plane and use vias to ground all critical components to this layer. the ground plane layer should not have any traces and it should be as close as possible to the layer with power mosfets. use an immediate via to connect the components to ground plane including gnd of UP9303 use several bigger vias for power components. 5 apply another solid layer as a power plane and cut this plane into smaller islands of common voltage levels. the power plane should support the input power and output power nodes to maintain good voltage filtering and to keep power losses low. also, for higher currents, it is recommended to use a multilayer board to help with heat sinking power components. 6 the phase node is subject to very high dv/dt voltages. stray capacitance between this island and the surrounding circuitry tend to induce current spike and capacitive noise coupling. keep the sensitive circuit away from the phase node and keep the pcb area small to limit the capacitive coupling. however, the pcb area should be kept moderate since it also acts as main heat convection path of the lower mosfet. 7 UP9303 sources/sinks impulse current with 2a peak to turn on/off the upper and lower mosfets. the connecting trance between the controller and gate/ source of the mosfet should be wide and short to minimize the parasitic inductance along the traces. 8 flood all unused areas on all layers with copper. flooding with copper will reduce the temperature rise of power component. 9 provide local vcc decoupling between vcc and gnd pins. locate the capacitor, c boot as close as practical to the boot and phase pins. application information
UP9303 17 UP9303-ds-f0101, aug. 2017 www.upi-semi.com note 1.package outline unit description: bsc: basic. represents theoretical exact dimension or dimension target min: minimum dimension specified. max: maximum dimension specified. ref: reference. represents dimension for reference use only. this value is not a device specification. typ. typical. provided as a general value. this value is not a device specification. 2.dimensions in millimeters. 3.drawing not to scale. 4.these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.15mm. package information sop-14l package 0.33 - 0.51 8.53 - 8.75 5.79 - 6.20 7.62 bsc 0.10 - 0.25 0.19 - 0.25 0.40 - 1.27 1.27 bsc 3.80 - 4.00 recommended solder pad layout 7.00 10 0. 1.50 10 0. 0.70 10 0. 1.27 10 0. 5.50 10 0. 4.00 10 0. 1.35 - 1.75
UP9303 18 UP9303-ds-f0101, aug. 2017 www.upi-semi.com important notice upi and its subsidiaries reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. upi products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment. however, no responsibility is assumed by upi or its subsidiaries for its use or application of any product or circuit; nor for any infringements of patents or other rights of third parties which may result from its use or application, including but not limited to any consequential or incidental damages. no upi components are designed, intended or authorized for use in military, aerospace, automotive applications nor in systems for surgical implantation or life-sustaining. no license is granted by implication or otherwise under any patent or patent rights of upi or its subsidiaries. copyright ( c ) 2016, upi semiconductor corp. upi semiconductor corp. headquarter 9f.,no.5, taiyuan 1st st. zhubei city, hsinchu taiwan, r.o.c. tel : 886.3.560.1666 fax : 886.3.560.1888 upi semiconductor corp. sales branch office 12f-5, no. 408, ruiguang rd. neihu district, taipei taiwan, r.o.c. tel : 886.2.8751.2062 fax : 886.2.8751.5064

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